With miniaturization of LSI, thinning of a gate insulating film has been in progress, and decreasing in gate capacitance owing to depletion of a polysilicon gate electrode cannot be disregarded. To solve this problem, there has been suggested substitution by a metallic gate electrode that is free from depletion (for example, refer to Japanese unexamined laid-open patent publication No. 2001-102443).
Generally, a source/drain is formed after formation of a gate electrode. However, compared to polysilicon, metal is much reactive to a silicon oxide film and a high-dielectric film such as Al2O3 or HfO2. Therefore, it is proposed to form a gate electrode after formation of a source/drain that needs high temperature treatment. These gates are called ‘Damascene-type gates’ or ‘replacing-type gates’ (for example, refer to A. Yagishita et al., IEDM Tech. Dig. (1998), pp.785–788, or A. Chatterjee et al., IEDM Tech. Dig. (1997), pp. 821–824).
FIGS. 44 to 54 are process diagrams for sequentially illustrating a conventional method for manufacturing a Damascene-type gate device and a replacing-type gate device.
First, as shown in FIG. 44, an element isolation 6a, a P-type well 8 and an N-type well 10 are formed on a semiconductor substrate 1. Then, a dummy gate oxide film 11 and a polysilicon film 12 are formed.
Next, as shown in FIG. 45, a resist pattern is formed using lithography, and dry-etching is carried out using the resist pattern as a mask, and dummy gates 12a are formed.
Next, as shown in FIG. 46, by lithography and ion implantation, a low concentration diffusion region 15 (hereinafter referred to as extension) of the NMOS, a pocket ion implantation region 16 (hereinafter referred to as halo) of the NMOS, and an extension 17 and a halo 18 of the PMOS are formed.
Next, as shown in FIG. 47, spacers 19 composed of a silicon nitride film are formed, and as FIG. 48 shows, a source/drain 20 for the NMOS and a source/drain 21 for the PMOS are formed.
Next, as shown in FIG. 49, a contact-etch stopper film 22 composed of a silicon nitride, film and an interlayer insulating film 23 composed of a silicon oxide film are formed.
Next, as shown in FIG. 50, the interlayer insulating film 23 and the contact-etch stopper film 22 are polished by chemical mechanical polishing (hereinafter referred to as CMP), and the upper surface of the dummy gates 12a is exposed.
Next, as shown in FIG. 51, gate trenches 25 are formed by removing the dummy gates 12a and the dummy gate oxide films 11 (refer to FIG. 50).
Next, as shown in FIG. 52, a gate insulating film 26 composed of a high-dielectric-constant insulating film such as Al2O3, HfO2, ZrO2 or the like, or composed of SiO2, SiN or the like, is formed so as to coat the inside of the gate trenches 25 (refer to FIG. 51). Then, a first metal film 27 composed of TiN or the like is formed. The first metal film determines the threshold value of the MOSFET, thus the material of the first metal film is chosen with consideration to work function and reactivity to the high-dielectric-constant film.
Further, so as to bury the trench, a second metal film 28 is deposited therein. The second metal is deposited so as to decrease the resistance of the electrodes, and material such as W, Al, Cu, or the like, which are used in normal wirings, would be sufficient.
Next, as shown in FIG. 53, in the case where a Damascene-type gate is to be formed, the Damascene-type gate 29 is formed by removing, using CMP, the second metal film 28, the first metal film 27 and the gate insulating film 26 that are deposited outside the gate trenches 25 (refer to FIG. 51).
Alternatively, in the case where a replacing-type gate electrode is to be formed, as shown in FIG. 54, instead of the process of FIG. 53, a resist pattern (not shown) is formed using lithography; the second metal film 28, the first metal film 27, and the gate insulating film 26 are selectively etched by dry etching using the resist pattern as a mask; and the replacing-type gate is formed.
Thereafter, interlayer insulating films are deposited on the Damascene-type gate or the replacing-type gate; and contacts and wirings are formed (graphic representation not given).
Now, FIG. 55 shows a sectional view of a conventional Damascene-gate type semiconductor device in a manufacturing process prior to CMP process for exposing the upper surface of the dummy gates. FIG. 56 shows a sectional view of a semiconductor device in a manufacturing process after CMP process for exposing the upper surface of the dummy gates. (FIG. 55 corresponds to the aforementioned process of FIG. 49, and FIG. 56 corresponds to the aforementioned process of FIG. 50 of the background art).
As shown in FIG. 55, the device includes regions 7, 9 and 14 on a P-type silicon substrate 1. In FIG. 55, the device includes, on a P-type silicon substrate 1, a region 7 on which an N-channel transistor is formed (hereinafter referred to as the N-ch region) and a region 9 on which a P-channel transistor is formed (hereinafter referred to as the P-ch region). Dummy gates 12a are formed respectively on the N-ch region 7 and on the P-ch region 9. The device includes a region 14 on which a dummy gate is not formed. Further, the device includes an element isolation 6a, a P-type well 8, an N-type well 10, a dummy gate oxide film 11, a contact-etch stopper film 22 and an interlayer insulating film 23.
As shown in FIG. 56, when the upper surface of the dummy gates 12a are exposed by CMP, the thickness of the interlayer insulating film 23 becomes thin after CMP due to dishing in the region 14 on which a gate for a transistor is not formed. As a result, a recess 35 appears. This is because the polishing speed of the contact-etch stopper film 22 and that of the interlayer insulating film 23 are different from each other.
Thereafter, as for the Damascene-type gate device, gate trenches are formed by selectively removing the dummy gates 12a and the dummy gate oxide film 11 formed under the dummy gates 12a. Then, a gate insulating film and a metal film are formed so as to fill the gate trenches, and the portion thereof formed outside the gate trench is removed again by CMP.
At this time, as shown in FIG. 57, the metal film 35a remains on the recess 35 (refer to FIG. 56), and short-circuiting of wirings is caused and change in interlayer capacitance occurs. Also, since CMP depends on the pattern or the occupation density of the dummy gates, control of the polishing amount becomes difficult.
Furthermore, also in the replacing-type gate device, a metal film may remain in a recess of an interlayer insulating film in a process for forming a contact plug, and the same problems as those in the Damascene-type gate device may arise.